The advent of the integrated circuit has spawned the necessity for automated testing to achieve rapid, accurate, and high volume results. Accordingly, automated test equipment (ATE) has been developed to maximize integrated circuit test efficiency, while minimizing the amount of human intervention that is required to complete a particular set of test scenarios.
A typical ATE includes a wafer probe station that secures a single integrated circuit, or a wafer containing multiple integrated circuits, into position to allow a device tester to exercise one of the integrated circuits using automated test sequences. More advanced ATEs provide the ability to implement test scenarios in parallel, whereby multiple integrated circuits may be exercised simultaneously. The integrated circuit, or wafer containing multiple integrated circuits, is often referred to as the device under test (DUT).
The DUT may exhibit a multitude of input/output (I/O) pad configurations, whereby any number of pads may be distributed in any number of configurations in accordance with the requirements of the particular DUT. The I/O pad configurations then allow the injection of test signals and the reception of the responses to those test signals from/to the ATE. Developers of ATE equipment, therefore, are challenged with the daunting task of designing ATEs that are compatible with as many I/O pad configurations as possible.
To improve compatibility, the corresponding wafer probe stations of the ATEs employ a probe card that acts as an interface between the ATE and the DUT. The probe card includes a probe head that is designed to be compatible with the I/O pads of the DUT while at the same time providing compatibility to the ATE. As such, the probe head includes a first set of test probes that are used to inject stimuli into the one or more input pads of the DUT. The probe head also includes a second set of test probes that are used to receive each DUT's response to the test stimuli injected by the first set of test probes.
The probe head, among other features, facilitates a mechanical translation between the fixed pin-out capabilities of the ATE, such as hard-wired input/output channels, into a flexible arrangement of probe pins that are compatible with the I/O pads of the DUT. In order to facilitate the mechanical translation, the probe head may be arranged as a vertical probe card such as a Cobra® probe card.
A Cobra® probe card implements a vertical probe design, whereby probe pins float in a substantially vertical direction 124 within probe head 114 as exemplified in FIG. 1. Vertical probe card 100 is exemplified as a vertical probe card that is comprised of printed circuit board (PCB) arrangement 126 and probe head arrangement 128. Vertical probe card 100 is illustrated in a disengaged state, such that probe needles 130 are separated from pads 104 of PCB arrangement 126 by separation distance 132.
Guide plates 110 and 116 are utilized within vertical probe card 100 to align probe needles 130 to their respective I/O pad connections. Probe tails 108 of probe needles 130, for example, are guided by top guide plate 110 through channels 112 so that proper engagement of probe tails 108 with pads 104 of PCB arrangement 126 is facilitated. In particular, movement of probe needles 130 in a substantially vertical direction 124 is facilitated by top guide plate 110 via channels 112 so that gap 132 is eventually closed to allow probe tails 108 to physically engage pads 104 during execution of a test scenario by the ATE.
Similarly, probe tips 120 of probe needles 130 are guided by bottom guide plate 116 so that proper engagement of probe tips 120 with pads (not shown) of DUT 134 is facilitated. In particular, movement of probe needles 130 in a substantially vertical direction 124 is facilitated by bottom guide plate 116 so that gap 136 is eventually closed to allow probe tips 120 to properly engage the DUT's I/O pads (not shown) during a test scenario.
It is noted that probe head 114 provides channels 122 to relieve a portion of the stress imposed upon probe needles 130 while probe needles are physically engaged with DUT 134 and PCB arrangement 126 during execution of the test scenario. In particular, channels 122 facilitate flexing of probe needles 130 upon engagement of probe tails 108 with pads 104 and upon engagement of probe tips 120 with DUT 134. Further, channels 122 facilitate proper engagement of probe tips 120 with DUT 134 even when the I/O pads of DUT 134 do not exhibit a uniform height in direction 124. Such may be the case, for example, when probe tips 120 are required to engage DUT pads implemented as, e.g., micro-bump configurations, that are utilized in conjunction with flip-chip bonding to subsequently bond the DUT's semiconductor substrate and the DUT's corresponding semiconductor package after successful testing of the integrated circuit is complete.
As discussed above, vertical probe card 100 is illustrated to be in a disengaged state, such that gap 132 exists between probe tails 108 and pads 104. Over an extended amount of time, a sufficient amount of oxidation, as well as other non-conductive contaminants, may collect on probe tails 108 during the disengaged state, such that even when probe tails 108 are engaged with pads 104, a sufficient amount of resistance exists between probe tails 108 and pads 104 to cause an open-circuit condition to be registered by the ATE during the test sequence. As such, a false indication is registered as a result of the open-circuit condition and the test scenario incorrectly fails due to the open-circuit condition.